1. Field of the Invention
The present invention relates generally to measuring signal path delays in an integrated circuit, and more particularly, to in-situ methods and systems for measuring signal path delay in an integrated circuit.
2. Description of the Related Art
Integrated circuits such as microprocessors include many signal paths. Each signal path has a signal delay that typically delays the signal being transmitted through the signal path. The signal path delay may be relatively very small or relatively quite large. The magnitude of the signal path delay is a function of many aspects of the signal path including a number of logic steps in the signal path, a process-type of each of the devices in the signal path, and a physical length of the signal path.
In an ideal integrated circuit, all of the signal paths would have the same signal path delay so that a clock signal can be accurately timed so as to detect the correct signal level at the correct time as the signal passes through the signal path. In a typical integrated circuit, the signal paths do not have the same delay and therefore the clock must be delayed by a selected time or number of degrees of the clock cycle (i.e. phase shifted). The clock delay is referred to as a guard band. An ideal guard band can very narrow, or even have a zero width, if all the signal paths have the same signal path delay. Conversely, if the signal path delays are different, then the guard band must be sufficiently wide to encompass the greatest signal path delay.
By way of example, FIG. 1A shows a typical microprocessor 120. The microprocessor 120 has four signal paths 122, 124, 126 and 128 between respective regions A and B, A and C, A and D, and A and E of the microprocessor. Each of the signal paths 122, 124, 126 and 128 has respective signal path delays of 0.8 ns, 0.2 ns, 0.4 ns and 0.4 ns. Therefore, the minimum signal path delay is 0.2 ns in signal path 124 and the maximum signal path delay is 0.8 ns in signal path 122. Therefore, the guard band for the clock must be at least 0.8 ns so that the clock signal does not transition (i.e., switch), so as to sample the signal levels on each of the signal paths 122, 124, 126 and 128 until all of the signal paths will have switched in the corresponding cycle of the respective signals.
As the guard band grows larger, the maximum frequency of the clock and the signal paths 122, 124, 126 and 128 must be reduced. By way of example, a 0.8 ns guard band limits the clock frequency to less than 1.25 GHz because 0.8 ns is equal to the wavelength of a clock signal at 1.25 GHz.
A semiconductor manufacturing process determines the process-type of a semiconductor device. The semiconductor manufacturing process can produce semiconductor devices operating across a performance range due to even slight variations in the semiconductor manufacturing processes. The performance range can occur between devices that are formed on different semiconductor wafers or devices that are formed on different parts of a single wafer or even devices contained in different parts of a single integrated circuit. By way of example, in a single manufacturing process, a first sense amplifier formed on a first semiconductor wafer may have a switching speed of about 20 percent faster than a second sense amplifier formed on a second semiconductor wafer. Similarly, a first sense amplifier formed on a first portion of a semiconductor wafer may have a switching speed of about 5 percent faster than a second sense amplifier formed on a second portion of the same semiconductor wafer. Typically sense amplifiers and other semiconductor devices are tested during the production process to determine if the component has a fast, slow or typical switching speed and the corresponding process-type classifications of a fast-type, a slow-type or a typical-type.
Unfortunately, the slow-type devices are often intermixed with the typical-type devices and the fast-type devices as described in FIG. 1A above. FIG. 1B is a schematic of the signal path 124. The signal path 124 includes a flip-flop 142 coupled through multiple logic stages 144, 146, 148 to a sense amplifier 150. The sense amplifier 150 can be a slow-type sense amplifier (i.e., has a slower than typical switching speed) and therefore signal path 124 is a slow-type signal path. Signal path 122 is a fast-type signal path (e.g., includes fast-type components). Signal paths 126 and 128 are typical-type signal paths (e.g., include typical-type components) but include different numbers of devices (e.g., logic gates, sense amplifiers, etc). As a result, each of the signal paths 122, 124, 126 and 128 has a different signal path delay.
However due to various dynamic factors (e.g., circuit temperature, circuit degradation over time, etc.) the signal path delays on each of the signal paths 122, 124, 126 and 128 can vary over time. Typically, this variation is projected and added to the required guard band. This further broadens the guard band and further reduces the maximum frequency of the clock signal.
Other types of signal paths such as between an I/O buffer and a register can also have respective signal path delays. By way of example, an I/O buffer can include many parallel signal paths (e.g., 128-bit I/O buffer can have 128 signal paths) between each I/O amplifier and the corresponding input register. As described above, each of the signal paths in the I/O buffer can have a different time delay, thereby requiring a corresponding clock guard band.
Signal path delays are typically measured using various testing circuits that are externally attached to the completed integrated circuit. However, the external testing circuits are cumbersome and cannot be used while the integrated circuit is in use to determine an actual signal path delay dynamically, while each of the signal paths are in use. Once the signal path delays are measured, a guard band is calculated as described above and is typically stored on the integrated circuit such as through fuses or other storage methods. In use, when the integrated circuit is initially activated (i.e., powered-up), the guard band for the clock is retrieved and the clock is then delayed accordingly. The external signal path delay testing circuit also cannot accurately measure the signal path delay as the testing circuit can also have some inherent delay.
In view of the foregoing, there is a need for a system and method for measuring the signal path delay that is included within the integrated circuit.